The subject matter disclosed herein relates to queuing of instructions in a processor and more particularly relates to shared compare lanes for dependency wake up in a pair-based issue queue.
A processor or core of a processor often include multiple execution slices that enable parallel processing of commands. The commands are compiled into instructions and a dispatcher sends instructions to an execution slice for processing. The instructions are processed by a mapper that tracks operations and data of an instruction and places the instructions in an issue queue, which verifies operands and other data inputs are available before execution of the instructions. In some cases, the mapper places instructions in a double issue queue where instructions can be paired in a row, which often is more efficient than a single-wide issue queue. While performance is enhanced by tracking all source dependencies for paired instructions, cost and complexity are increased.